IEC 60749-41-2020 pdf download.Semiconductor devices – Mechanical and climatic test methods – Part 41: Standard reliability testing methods of non-volatile memory devices.
The apparatus required for this test shall consist of a controlled temperature chamber capable of maintaining the specified temperature conditions to within ±5 °C. Sockets or other mounting means shall be provided within the chamber so that reliable electrical contact can be made to the device terminals in the specified circuit configuration. Power supplies and biasing networks shall be capable of maintaining the specified operating conditions throughout the test. Also, the test circuitry should be designed so that the existence of abnormal or failed devices will not alter the specified conditions for other units on test. Care should be taken to avoid possible damage from transient voltage spikes or other conditions that might result in electrical, thermal or mechanical overstress.
5 Procedure
5.1 Qualification specifications Qualification specifications, including those in JESD47, commonly require that some devices undergo endurance cycling followed by retention stressing. There may also be retention requirements for uncycled devices and for the optional cross-temperature testing across the temperatures specified in the data sheet. Qualification specifications commonly call for endurance cycling to be performed at multiple temperatures within the datasheet range, and retention stress to be performed both at elevated temperatures, such as 1 25 °C, and room temperature. Figure 1 schematically illustrates the flow, with references to the paragraphs describing the procedure.
A supplementary test condition is given in Annex A.
5.2 Program/erase endurance
5.2.1 Test setup Devices shall be placed in the chamber so there is no substantial obstruction to the flow of air across and around each unit. The power shall be applied and suitable checks made to assure that all devices are properly energized. When special mounting or heat sinking is required, the details shall be specified in the applicable device specification and/or test specification.
5.2.2 Data cycling
5.2.2.1 Program and erase verification Program and erase operations during the endurance test shall be verified to have been properly executed in accordance with the device specification or the supplier’s internal stress test specification (see Clause 7).
5.2.2.2 Data patterns during cycling The data pattern used for endurance cycling shall be agreed upon between supplier and user, and the rationale documented. It is important to cycle enough sectors of blocks during the cycling period taking into account for the target application models. See Note 1 to Entry 3.4 for a discussion of the trade-offs involved in the selection of data pattern for cycling. The purpose of many qualifications is to test the device for the broadest possible range of failure mechanisms. The broadest possible range of failure mechanisms can be detected when the data pattern includes the full range of logic levels and adjacency conditions that would occur in actual use. For example, this full range can be achieved if the following three conditions are met. First, the data in the memory cells is cycled between all available logic states in equal measure. For example, in an SBC memory half the cells would be programmed and half left erased in any one cycle, whereas in a 4-level cell memory one-quarter of the cells would be written to each of the four available levels in any given cycle. Second, the positions of 1 s and 0s are non-uniform, ideally quasi-random, so that all possible adjacency configurations are represented. For example, a data pattern consisting of a mix of bytes with data patterns 00H (zero zero hexadecimal), 55H, AAH, 33H, CCH, and FFH would create a wide range of adjacency patterns. Third, the data pattern in successive cycles is not the same, but rather follows a sequence. Best practice is to ensure, in this sequence, that some cells are written to all available logic states while other cells are re-written to the same logic state in every cycle. For example, in an SBC memory, a byte that was cycled to AAH in even- numbered cycles and 5AH in odd-numbered cycles would have four cells that would be written to 0s and 1 s in alternating cycles, two cells that are re-written to 0 in every cycle, and two cells that are re-written to 1 in every cycle. In some knowledge-based qualifications, endurance tests can be defined for specific failure mechanisms. Such tests can use different data patterns from that described above, optimized to increase the sensitivity to the targeted mechanisms. Examples of acceptable data patterns for such purposes include a solid programmed pattern, checkerboard/inverse-checkerboard sequence, and checkerboard with subsequent filling-in of the pattern. Some flash EEPROM devices employ a built-in scrambling mechanism. When testing endurance of such devices, the scrambling mechanism should be enabled; disabling the scrambler for endurance cycling can stress the product beyond the stress a user can experience. A quasi-random pattern is best for testing endurance when employing scrambling.IEC 60749-41 pdf download.