IEC 62889-2015 pdf download.Digital video interface – Gigabit video interface for multimedia systems.
6 Front-end
6.1 General
The front-end block diagram of GVIF is shown in Figure 4.
6.2 TX front-end The TX front-end consists of a termination circuit, a down-stream driver and an up-stream receiver. The termination circuit consists of 2 resistors RL, and the SDATAP/N differential signal is pulled up to voltage reference (VDD) with a (50 ± 1 5) Ω resistor. The down-stream driver consists of a differential current output circuit that is driven by the serial signal from the encoder. The up-stream receiver detects the common-mode signal which RX sends through the shielded twisted pair line. The input to the down-stream driver has two modes. One is the serialized actual encoded video data input mode and the other is the reference clock signal for REFREQ hand-shake input mode. These two modes activate depending on the common- mode signal level. The common-mode signal level is normally high. When a long low level pulse is detected, the up-stream receiver activates the REFREQ signal, and changes a mode of the encoder into the reference clock mode. In case of the optional up-stream user data transmission, the up-stream receiver outputs the common-mode voltage as an UDA signal by using binary digital data sent to the encoder. In this case, the upper limit of the low pulse time is 1 00 µs.
6.3 RX front-end The Rx front-end consists of AC capacitors, a termination resistor RT (1 00 ± 5) Ω, a down- stream receiver and an up-stream driver. The down-stream receiver consists of a differential input detection circuit which receives the transmission potential differential signal through the shielded twisted pair line. The up-stream driver drives the up-stream transmission signal applying a current through the termination resistor Rx through the shielded twisted pair transmission line. (A recommended transmission system and transmission line for electrical characteristics is specified in Clause 5.)
7 Transition state link
The transition state link of GVIF shall meet the procedure described below.
There are two states in the connection link between GVIF TX and GVIF RX. One is the state transmitting differential signal with a reference clock, the other is the state transmitting the H format word or the C format word. In the former state, the TX encoder is in the reference clock output mode and the RX decoder is in the reference clock request mode. In the later state, the TX encoder changes into the encoder mode and the RX decoder changes into the decoder mode. The state transition switching diagram of the encoder and the decoder is shown in the Figure 5.
8 Protocol
8.1 General
The encoder encodes the 30 bit of data (P[23:0], HSYNC, VSYNC, DE, CNTL, SDA and TDA) in synchronization with the input of SFTCLK, and outputs 1 bit of the serial signal S to the TX front-end.
To ensure the DC balance data and a reasonable transition, it is required to generate a synchronization pattern for each word in synchronization with the falling edge of HSYNC at the receiver.IEC 62889 pdf download.