IEC 60424-3-2015 pdf download.Ferrite cores – Guidelines on the limits of surface irregularities – Part 3: ETD-cores, EER-cores, EC-cores and E-cores.
This part of IEC 60424 gives guidelines on allowable limits of surface irregularities applicable to ETD-cores, EER-cores, EC-cores and E-cores in accordance with the relevant general specification. This standard is a specification useful in the negotiations between ferrite core manufacturers and customers about surface irregularities.
2 Normative references The following documents, in whole or in part, are normatively referenced in this document and are indispensable for its application. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.
IEC 60424-1 1 , Ferrite cores – Guidelines on the limits of surface irregularities – Part 1: General specification
IEC 60647, Dimensions for magnetic oxide cores intended for use in power supplies (EC- cores)
IEC 61 1 85, Ferrite cores (ETD-cores) intended for use in power supply applications – Dimensions
IEC 6231 7-7, Ferrite cores – Dimensions – Part 7: EER-cores
IEC 6231 7-8, Ferrite cores – Dimensions – Part 8: E-cores
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1 pore hole left on the surface of cores after sintering and surface finishing
3.2 crystallite grain of abnormal size distinguishable on the surface, often with sparkling facets
4 Limits of surface irregularities
4.1 Chips and ragged edges
4.1.1 General
Chips and ragged edges are defined in IEC 60424-1 .
4.1.2 Chips and ragged edges on the mating surfaces
The areas of the chips located on the mating surfaces (chip1 and chip1 ′ irregularities of Figures 1 and 2) shall not exceed the following limits:
– the cumulative area of the chips shall be less than 6 % of the mating surface (whether gapped or ungapped) of the centre leg;
– the total length of the ragged edges shall be less than 25 % of the perimeter of the relevant surface.
4.1.3 Chips and ragged edges on other surfaces
The allowable areas of chips are doubled as compared to the limits for the mating surface (see Table 1 for ETD-cores, Table 2 for EER-cores, Table 3 for EC-cores and Table 4 for E-cores).
The rule for ragged edges is the same as for the mating surface.
The allowable areas of chips for a given core are summarized in Tables 1 , 2, 3 and 4.
The core sizes given in Tables 1 and 2 correspond to the cores defined in IEC 61 1 85,IEC 6231 7-7, IEC 60647 and IEC 6231 7-8.
4.2 Cracks
Cracks are defined in IEC 60424-1 .
The limits for cracks at various locations shown in Figures 3 or 4 are given in Table 6.
4.3 Flash
Flash is defined in IEC 60424-1 .
There shall be no flash extending from the core into the wire-slot.
4.4 Pull-outs
Pull-outs are defined in IEC 60424-1 .
For ETD-cores, EER-cores and EC-cores the cumulative area of pull-outs of the core shall be less than 25 % of the total area of bottom surfaces.
For E-cores the cumulative area of pull-outs of the core shall be less than 25 % of the total area of a side surface.IEC 60424-3 pdf download.